Threshold voltage for n-FET and p-FET
Submitted by SDRAM Technology on Thu, 10/08/2009 - 11:54
The threshold voltage (Ut) of a Field Effect Transistor (FET) is the voltage applied on the gate of the transistor at which a measurable current between source (S) and drain (D) is starting to flow. At this voltage an inversion layer under the gate (between source and drain) is formed, so that the pn-junctions (immediately under the gate) are vanishing and thus a current path between drain and source is obtained. The resistance of these this current path (inversion layer) depends on the thickness of the layer, which is determined by the applied gate voltage. A schematic overview of measurement setups for threshold voltages of N-FET and P-FET transistors is presented in Figures 1 and 2.
Figure 1: Measurement of the N-FET thershold voltage
Figure 2: Measurement of the P-FET thershold voltage
There are two types of threshold voltages: Linear and Saturated
- Linear: For small source-drain voltages the current increases linearly with the gate voltage. In this case Ut is the intersection of the linear extrapolation of the IDS vs. UG curve with the UG-axis (see Figure 3).
- Square Ut (saturated region): For large source drain voltages the IDS current is not linear with the gate voltage, but has a square behavior (see Figure 4a). If you plot sqrt(IDS) vs. UG then you can again determine the threshold voltage as explained for the linear case (see Figure 4b).
The substrate (Ust) or N-well (UN-well) voltage affects the threshold voltage. This is known as the substrate sensitivity, which depends on the doping in the gate area.
Figure 3: Linear threshold voltage of a FET
Figure 4: Squar / Saturation Threshold Voltage of a FET Transistor
Why is threshold voltage so important?
- Speed of circuits: If the threshold is too high, then the circuit is too slow. The circuits always contain parasitic capacitances that must be charged before the voltage can increase so that the transistor opens and consequently can charge for example the next stage of a circuit.
- Symmetry: For complementary MOS circuits the threshold voltages of N-and P-channel transistors must be equal (with opposite signs).
- Reliability: If Ut is too low, then the transistor can not be properly turned off. In SDRAM memory chips, the information is stored in a capacitor that is connected via a transistor to the bit line. If the threshold voltage of this transistor too low, then the memory-cell information is lost too quickly and a reliability problem occurs. Since all transistors lose something of their threshold voltage by aging, the initial Ut must not be too low. A compromise between a, b and c should be always found.
How can be the threshold voltage influenced?
- by gate oxide thickness: The threshold voltage is directly proportional to the thickness of the gate oxide. This thickness can be determined from the electrical capacitance of a specially designed capacitor in the test structures.
- by impurities: The so called flat-band voltage is directly proportional to the threshold voltage and can be influenced by electrically charged impurities in the gate oxide. By measuring the flat-band voltage you can check whether the deviation of Vt from the set-point is due to contamination or not. These impurities occur usually during the cleaning processes before gate-oxide growth or during the gate-oxide growth itself.
- by doping: If the previous two points can be excluded, there remains only the doping in the gate region as a reason for threshold voltage deviations. The doping in the gate region is produced by various implantation steps. Doping by implantation is essentially the main way for manipulating intentionally the threshold voltage of FET transistors. A higher net doping increases the threshold voltage. This is plausible because it requires a higher voltage to invert the area below the gate electrode.