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Test structures on SDRAM wafers

A SDRAM chip contains a lot of structures like pn-junctions (diodes), transistors, resistors, P/N-walls etc. In order for a chip to function well the structures enumerated before should fulfill some criteria specified by the designers of the chip. Thus, methods are needed to measure the properties of “transistor & Co” in order to see if the manufactured structures fulfill the specified criteria.

However, in order to measure the parameters of a structure, e.g. of a transistor, a number of pads are required in order to be able to connect the transistor to an external measurement tool. Evidently it is not possible to make pads directly on the chip for each transistor which is supposed to be measured, because the pads will require a lot of space (remember that the space is limited on a SDRAM chip).

The solution is to make a number of so called “test structures” not directly on the chip, but between the chips. As described in the article "Chip Level Assembly", during the so called dicing process the chips are cut apart as separate components. In order to be able to perform the dicing process, without to destroy the chips, some “unused space” between the chips should be present on the wafers. Thus, this “unused space” can be made usefull and put the test structures with their space consuming pads (see Figure 1).

Test structures on SDRAM Wafers

Figure 1: Where are pleaced the test structures on a SDRAM Wafer?

Due to the fact that the structures on the chip itself and the test structures between the chips will see the same microelectronic manufacturing processes, it is expected that the parameters of test structures will reflect/represent the parameters of structures from the chip.

Certainly, the test structures will be destroyed during dicing. However, the test structures are measured and evaluated long before the dicing process takes place. Destroying the test structures is even beneficial for the chip producing company, because the competitors will not have the possibility to see which test structure are used in order to control the manufacturing process.