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Threshold voltage for n-FET and p-FET

The threshold voltage (Ut) of a Field Effect Transistor (FET) is the voltage applied on the gate of the transistor at which a measurable current between source (S) and drain (D) is starting to flow. At this voltage an inversion layer under the gate (between source and drain) is formed, so that the pn-junctions (immediately under the gate) are vanishing and thus a current path between drain and source is obtained. The resistance of these this current path (inversion layer) depends on the thickness of the layer, which is determined by the applied gate voltage. A schematic overview of measurement setups for threshold voltages of N-FET and P-FET transistors is presented in Figures 1 and 2.

What is leakage current of a pn-junction and how to measure it?

A leakage current is the current which is flowing thought a pn-junction when is inversely polarized. As the definition says in order to measure the leakage current of a pn-junction you simply have to apply a voltage in the reverse direction of the junction and measure the resulting current. A schematic picture of this process is presented in Figure 1.

What are Retention Time and Tests for SDRAM memory?

As already mentioned in the article SDRAM elementary cell, the DRAM components (i.e. the transistor and the capacitor) are not ideal and the information (charge) can leak from/into the capacitor and destroy the information inside the DRAM cell. Charge leakage occurs mainly due to imperfection of the capacitor and of the p-n-junctions making the transistor (source and drain). A schematic representation of how the charge can leak is presented in Figures 1 and 2. As a result of charge leakage the DRAM memory cells have to be often refreshed in order to avoid loosing information. Due to this refreshing procedure the DRAM is called Dynamic RAM (random access memory), i.e. the charge can not stay in the capacitor forever and should be dynamically refreshed.

SDRAM Yields: What are these?

The SDRAM chips are manufactured on silicon wafers. Depending on the size of the chips and the size of the wafer a different number of chips can fit on one wafer. The state of the art wafers in microelectronics are at the moment (year 2009) the so called “300 mm wafers”, which certainly means that the diameter of the wafer is 300 mm. Depending on the technology node (90nm, 70nm, 60nm etc.) and the bit capacity of a SDRAM chip (512 Mb, 1Gb, 2Gb or even 4 Gb) the number of chips which can fit on one wafer can vary strongly. A typical SDRAM chips size is 30-50 mm2 and thus on a 300mm wafer can fit more that 1000 chips. A relatively high number taking into account that a normal SDRAM DIMM or SODIMM module needs 8, 16, 32 etc chips to be build.

Back End Test Flow Overview

In one of the last articles I discussed the purpose of the Back End Test, in this article I will shortly describe what are the stages of a Back End Test. A Back End Test is done on the chipe level and can have the following test stages (see also Figure 1):

Purpose of the SDRAM Back End Test

As was mentioned in the Chip Level Assembly and SDRAM Factory Schematics articles, after the chips assembly the chip is normally tested again. This test at the chip level is called the Back End Test. The main purpose of the back End Test is to find chips which are:

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