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What are Retention Time and Tests for SDRAM memory?

As already mentioned in the article SDRAM elementary cell, the DRAM components (i.e. the transistor and the capacitor) are not ideal and the information (charge) can leak from/into the capacitor and destroy the information inside the DRAM cell. Charge leakage occurs mainly due to imperfection of the capacitor and of the p-n-junctions making the transistor (source and drain). A schematic representation of how the charge can leak is presented in Figures 1 and 2. As a result of charge leakage the DRAM memory cells have to be often refreshed in order to avoid loosing information. Due to this refreshing procedure the DRAM is called Dynamic RAM (random access memory), i.e. the charge can not stay in the capacitor forever and should be dynamically refreshed.

Schematic representatio of charge leakage in a DT based SDRAM cell

Figure 1: A schematic representation of charge leakage in a DT (deep trench) based SDRAM cell.

Schematic representatio of charge leakage in a SC (stack capacitor) based SDRAM cell

Figure 2: A schematic representation of charge leakage in a SC (stack capacitor) based SDRAM cell.

According to the JEDEC standard a DRAM cell must keep its information/charge for a minimum time of 64 ms. By “keeping its information” it is meant that the cell after every 64 ms still must have enough charge inside it so that this charge will be recognized correctly (as “1” or “0”) by the so called sense amplifiers.

The 64 ms are recommended by JEDEC, however the DRAM cells do not know “the standards” and therefore, they can keep their charge inside them longer or shorter than 64 ms. Thus, the time which a DRAM cell is able to keep its charge /information inside it, so that when reading this cell (after this time) the information inside the cell is still interpreted correctly (by the sense amplifier) is called Retention Time for this cell. Retention time of 64 ms is one of the most important parameters which a DRAM cell has to fulfill!

For example, when saying that a DRAM cell has a retention time of 256 ms, this means that this cell is able to keep its correct information inside its capacitor for at least 256 ms. According to JEDEC in a, for example, 1 GB chip, ALL (without exception) 1.000.000.000 cells (cells which can be addressed) should have a retention time which is bigger that 64ms. The retention time for all cells on a DRAM chip is determined during the test procedure of DRAMs, i.e. Front End or Back End tests.

Due to the fact that a cell can have a different retention times for “0” and “1”s, retention times for “0” and “1” can be distinguished as well. More than that, the retention time of the cells can be influenced by the temperature of the chip, by the information which is stored in the neighboring cell (yes, a cell can have a different retention time for example for “1” if its neighboring cells have also “1”s inside, as when the neighboring calls have “0” inside), by the used technology (70nm, 60nm etc or trench vs. stack capacitor technology), chip size etc, etc. Due to this fact a special testing strategy must be developed in order to find out all cells which have a bad retention time and which do not fulfill the JEDEC retention requirements.

In order to be sure that the JEDEC requirements will be fulfilled, the DRAM companies normally use a guard band for the retention time and require that the cells on their chips should have retention times of, for example, at least 256 ms. The guard band is necessary because the retention of the cells can change in time (due to degradation) and with a guard band it is less probable that the retention time of the cells will go below the required by JEDEC 64 ms.

A good strategy for retention testing is not easy to develop. The reason for this is that you always must find a compromise. If you will choose a very aggressive strategy, i.e. retention tests will be very exigent, then the tests will find a lot of cells which do not fulfill the conditions of your tests (e.g. retention >256 ms) and thus all these cells must be repaired by means of the redundancy (I will explain in a later article what redundancy means, for the moment it is enough to know that a “bad” DRAM cell can be “exchanged” by a “good” cell). Due to the fact that on one chip you have a limited number of redundant cells you can repair (i.e. exchange) only a limited number of retention bad cells. If your retention tests will find 10.000 “bad” retention cells, but you can repair only 2000, then you have a problem: your chip must be scraped due to the fact that it does not fulfill your test requirements.

On the other hand if your retention tests are too relaxed you will not be able to find all potentially bad cells and thus your chip could be good after the Front End Test, but will fail in the Back End Test. So, your retention test strategy in Front End should be good enough so than on one side not many chips will fail in Back End testing, on the other side not so many chips will be scraped after the Front End test. Not easy!