Skip navigation.
640K will be enough for anybody...

Registered and Stacked SDRAM Modules

For synchronous DRAM (SDRAM) unbuffered, registered and stacked modules are usual. In the following I will explain what registered and stacked modules are:

Registered modules: In general can be said that registered modules are actually more developed buffered modules. As in the case of buffered modules the addresses and commands go via a buffer which in this case is called Register. EDO and FPM modules have an asynchronous timing, thus it is acceptable that the delay between address/command and data signals to be controlled and balanced by the computer and is not a big problem if address/command and data signals have a phase shift between them. In the case of SDRAM modules the situation changes, they have a synchronous timing and are usually also faster, so that the delay between address/command signals and data signal can vary only to a very small extent.

In order to solve this problem an additional chip, the so called PLL (Phase Locked Loop), will mounted on a registered module. The clock signal from the computer goes only to the PLL, the control signals (address/command) go to the register. However, the control signals are released by the register only when a signal from PLL is given. The clock signal which goes to the chips is also generated by the PLL. In this way it is possible to manage the delay between the control and data signals with a high precision. However, due to PLL the speed of the module is negatively influenced. The control and address signals in registered DIMMs are delayed during the "read process" by one tact relative to the data signals, which is similar to an increased latency. On the other hand, at during the "write process" the computer shall delay the data also by one tact, so that the commands and data will reach the chips simultaneously.

SDRAM Registered Module example

Figure 1: SDRAM registered module

Stacked modules: A stacked module is only a special form of registered modules. Register and PLL chips still exist as in the case of a pure registered module. The difference is only that in the case of stacked module two SDRAM chips are stacked one above another. This doubles the storage capacity per module and the module becomes a two bank module. The communication with the upper and lower chips is done via the chip select signals, which are separated for the top and bottom chips. Due to the fact that the stacking of chips is not very well controlled and do not allows the modules to be repaired this process turns to be a costly one.