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Buffered and Unbuffered DRAM Modules

For non-synchronous DRAM, like EDO/FPM, buffered and unbuffered modules were usual. What is the difference actually between unbuffered and buffered DRAM modules?

Unbuffered modules: The module-DQs pins (DQ = data query) are connected with the chip-DQ pins directly through resistors. The address and command module pins are directly linked to the corresponding chip pins as well. The CS and Clock signals go usually to 4-5 chips in parallel. The DQMB signals to 1-3 chips, while all other commands and addresses go in parallel to all chips.

Buffered modules: If a computer has many modules to control in parallel, then it has to control the addresses and commands of all chips on these modules simultaneously. This represents a very high capacitive load, which a computer can not drive alone. In order to solve this problem a small amplifier or buffer shall be placed on the circuit boards of the module (see Figure 1), through which the addresses and commands will run. In this way the computer has to drive and control only a small amplifier/buffer instead of several chips, while the address and command signals for the chips will be controlled by the amplifier. Of course this means a delay for the signals which are controlled by the amplifier. Note that the DQ pins are not buffered, since each DQ goes to only one chip. Therefore, the computer shall take into account this delay for address and command so that they will reach the chips at the same time as the data, i.e. DQ, signals.

 Buffered DRAM module

Figure 1: Buffered DRAM module