Skip navigation.
640K will be enough for anybody...

What are bit-lines and word-lines on a SDRAM chip?

As discussed in “SDRAM Chip Architecture / Structure: Array and Periphery” article the smallest memory-array unit of a SDRAM chip is the array-segment. An array-segment is a two dimensional array consisting normally of 512 x 512 bits, or can be bigger depending on the used technology (see Figure 1). As with any array in order to access one of its elements, in our case a memory cell, you have to specify the raw-number and column-number. The intersection point of the specified row-column pair will be the addressed element (Figure 1).

2D <array-segment schematics

Figure 1: Array-segment schematics

In SDRAM terminology the rows are called word-line, whereas the columns are named bit-lines. Physically the word-lines are represented by the so called “gate-contact lines” (GC-lines), which are “metallic” or “poly-Si” (or combination of both) stripes. They are connecting the gates of all transistors of a certain raw in the array-segment (see Figure 2). Thus, when activating / deactivating a word-line, i.e. increasing/decreasing the voltage on/from it, ALL transistors which are on this raw of the array-segment will open or correspondingly close.

Wordlines and wordline-drivers

Figure 2: a) Wordline and wordline-drivers schematics; b) Scanning Electron Microscope view of real WL (GCs), top view

The voltage of each word-line is raised (transistor ON) and lowered (transistor OFF) by the so called word-line drivers (WLD), see Figure 2. The higher the number of transistors connected to one word-line driver, i.e. the bigger the array-segment is, the higher the capacitance of the word-line and consequently more powerful should be the word-line driver in order to control the word-line. If the word-line driver is not powerful enough it can happen that the transistors at the end of the word-line (faraway from the word-line driver itself) will not become the necessary potential in order to be opened properly. The word-line drivers can not be made powerful enough to drive a very long word-line due to space limitation on the chip. A more powerful word-line driver will need more place on the chip and thus will decrease the array efficiency of the chip. The designers should find a compromise between the length of the word-line and the size of the word-line driver.

Bit-lines are “metatlic” stripes perpendicular to the wordlines and are physically connected to the source/drains of the cell-transistors. In other words, the bit-lines are the lines through which information is  written/read to/from the memory cells. Information is read from the cell, or written into the cell by the so called sense-amplifiers - each bit-lne is conected to a sense-amplifier (SA, see Figure 3). As with wordline-drivers, the sense-amplifiers can not be made too big, i.e. to be high performant, due to place limitations on the chip. However they should be good enough in order to read and write the information into the cells correctly. A trade off is needed as well.

 

Bitlines and sens-amplifier

Figure 3: a) Bitlines and sense-amplifiers schematics;  b) Scanning Electron Microscope view of real BLs (top view)

How schematically an array-segment looks like when the BLs, WLs, WLDs and SAs are connected to it is presented in Figure 4. Note that there is no direct contact between BL and WLs, the ar eon different levels when looking in coross-section. 

Array Segment Schematics of SDRAM

Figure 4: a) An array-segmen with BL, WL, WLDs ans SAs; b) WLs and BLs are on different levels, therefore no contact between them exists (Scanning Electron Microscope cross section view);