SDRAM Chip Architecture / Structure: Array and Periphery
Submitted by SDRAM Technology on Tue, 08/18/2009 - 14:45
SDRAM chip design is varying strongly from company to company, technology node to technology node and can also depend on the chip capacity (512 Mb, 1Gb, 2Gb etc.). The architecture is defined by the chip designers taking into account the particularities of the designed chip (see Figure 1 and 2). However, independent from the factors named above a SDRAM chip can be divided in two main parts:
- and Periphery
Array is the area on the chip where the SDRAM elementary cells are implemented. The array is not a monolithically defined structure, but is normally divided more array banks. An array bank is also divided in smaller areas called array segments (see Figure 1).
On the other hand, periphery is the area on the chip where the chip supporting structures (no SDRAM cells) can be found. The periphery can be also divided in chip periphery and array periphery. The chip periphery contains normally the pads of the chip, address and bank control logic electronics, generators for internal voltages etc.
The array periphery contains the logic electronics which is directly connected to the SDRAM elementary cells in the array: the so called word-line drivers and sense amplifiers. The chip periphery usually separates the array banks and the chip periphery separates the array segments from each other.
Figure 1: Example of a SDRAM chip architecture /structure.
On of the most important figure of merit of a SDRAM chip is the so called array or cell efficiency, which is the ratio between the area of the array and total area of the chip. The array/cell efficiency is normally expressed in percents. Typical values are 60 -70%, which means that the array, i.e. the actual memory, occupies 60-70% of the chip. The companies certainly are trying to increase the cell efficiency to the maximum, i.e. to minimize the periphery, due to the fact that it does not contribute to the memory capacity of the chip.
Figure 2: Another example of a SDRAM chip structure.